Conventional serial compressed data buses are dedicated to a single compressed data stream. Moreover, such buses require at least 3 to 4 pins. A typical 3 wire interface consists of a serial data signal, a clock signal and a sync or framing signal. The data is delivered in packets that are of a fixed size and the first bit of a packet is indicated by driving the sync or frame signal active.
An alternate 3 wire interface replaces the sync signal with a valid signal. The valid signal indicates when data is valid on the interface. As with the previous interface, this interface also requires packets to be of a fixed length. The first bit of a packet is indicated by driving the valid signal active. The valid signal is then required to remain active for the duration of a packet and is driven low at the end of the packet. When the valid signal is inactive, the data is ignored by the receiving device. Since the active edge of the valid signal is used to indicate the first bit of a packet, the valid signal must be driven inactive for at least one bit time between packets.
A widely accepted serial transport interfaces uses 4 wires to deliver data, clock, sync and valid signals. Like the 3 wire interface, the sync signal is driven active to indicate the first bit of a packet. Similarly, the valid signal is used to identify when data is valid on the interface. This approach gives the added flexibility that data gaps may exist within a packet time. Also, since the sync signal indicates the start of a new packet, there is no requirement for a gap between consecutive packets.
Given the current state of the art, there is a need for a serial compressed data bus that delivers more than one single compressed data stream. Moreover, there is a need for a serial compressed data bus interface having a reduced number of pins with respect to that required by conventional serial compressed data buses.